To date, deep trenches are extensively used in the manufacture of integrated circuits (ICs) and in particular in the manufacture of 64 and 256 Mb and will be probably used up to 1 Gb EDO and SDRAM memory chips in the future to define the storage capacitor of each memory cell. Basically, a deep trench is formed in a slightly doped silicon substrate, then a thin dielectric film is conformally deposited thereon to coat the entire interior trench surface and finally, the trench is filled with doped polysilicon. This silicon substrate/dielectric film/doped polysilicon composite structure forms the cell capacitor. To keep an acceptable capacitor value in spite of continuous size reduction, the thickness of the dielectric film is constantly reduced. In turn, the voltage across the dielectric film must be drastically reduced to avoid undesired voltage breakdown effects. In order to achieve this voltage reduction, a doped area is created in the silicon substrate around the bottom of the cell capacitor. This area is commonly referred to as the "buried plate" (BP) region in the technical literature. To that end, an arsenic silicon glass (ASG) film is conformally deposited onto the chip surface to coat the trench side wall and will be subsequently used to generate the arsenic (As) atoms to heavily dope the silicon substrate in order to create these BP regions. Then, after several processing steps which are necessary to set the buried plate region depth from the top trench surface, the As atoms are out diffused from the ASG film into the silicon substrate during an anneal. A conventional buried plate region formation process specifically includes the eight basic steps recited below.
1--Etching deep trenches in a p-type silicon substrate coated with a patterned pad stack comprised of a bottom silicon oxide (SiO2) layer and a top silicon nitride (Si3N4) layer as standard. PA0 2--Depositing a conformal ASG film onto the structure to coat deep trench side walls. PA0 3--Filling the deep trenches with a planarizing medium such as a photoresist. PA0 4--Removing the photoresist down to a given depth into deep trenches. PA0 5--Removing the ASG material from unprotected areas. PA0 6--Stripping the photoresist material remaining into deep trenches and then, depositing a conformal SiO2 layer onto the structure. PA0 7--Out diffusing arsenic atoms from the ASG film into the silicon substrate. PA0 8--Finally, removing SiO2 and ASG materials from deep trench side walls.
FIG. 1A schematically illustrates the starting structure 10 consisting of a p-type silicon substrate 11 with a 10 nm thick silicon oxide layer 12 and a 220 nm thick silicon nitride layer 13 formed thereon. These two layers will be referenced to hereinbelow as the SiO2/Si3N4 pad layer 12/13. As apparent in FIG. 1A, a deep trench referenced 14 has been formed in the substrate 11 by RIE etching as standard. Typically, deep trench 14 has a depth of about 7 .mu.m and an oblong section of about 550.times.320 nm at the substrate surface.
Now, turning to FIG. 1B, an arsenic silicon glass (ASG) is conformally deposited by LPCVD to coat the interior trench side wall with a 45 nm thick film referenced 15. As known for those skilled in the art, As atoms contained in ASG film 15 will subsequently act as N type dopants. This step is performed in a deposition equipment such as a vertical hot dual wall SVG 7000+LPCVD reactor manufactured and sold by SVG THERMCO, Orange, Calif., USA, schematically illustrated in FIG. 3 that will be detailed later on. The reactive atmosphere includes tetraethylorthosilicate (TEOS) and triethylarsenate (TEASAT) gases.
Then, a 1.8 .mu.m thick layer of a planarizing medium, typically a photoresist, is conformally deposited onto the structure in order to fill the deep trench 14 in excess. A photoresist such as AZ7511 manufactured by CLARIANT, Brunswick, N.J., USA, is adequate in that respect. As shown in FIG. 1C, after reflow, the photoresist layer bearing numeral 16 has a planar surface.
After photoresist reflow was performed, a given amount of the photoresist material is removed by a conventional lithographic process, so that the surface of photoresist layer 16 stands at about 1.5 .mu.m below the structure surface. The remaining material of photoresist layer 16 exhibits a typical recessed shape at its upper surface in trench 14 as shown in FIG. 1D.
Now, the unprotected portions of the N+ doped ASG film 15 are removed by wet etching in a buffered HF bath. An overetching occurs during this wet etch step at the top annular portion of the ASG film 15 to produce the moat or dip out 17, as apparent in FIG. 1E.
Next, the photoresist material remaining at the bottom of deep trench 14 is stripped by wet etching in a Huang SP solution and a 25 nm thick SiO2 layer 18 is conformally deposited by PECVD onto the structure to coat the deep trench side wall. An AME 5000 tool commercially available from Applied Materials Inc., Santa Clara, Calif., USA is appropriate. After these two process steps have been performed, the structure 10 is shown in FIG. 1F.
The structure 10 is then heated to diffuse the As doping atoms trapped in the ASG film 15 into the adjacent portions of the silicon substrate 11 to create the buried plate region 19. At this stage of the BP region formation process, the structure 10 is shown in FIG. 1G.
After the As dopant out diffusion step is achieved by adequate annealing conditions in the SVG 7000+ reactor to reach the desired junction (or diffusion) depth of at least 0.25 .mu.m. The ASG film 15 and the SiO2 layer 18 are removed by means of an appropriate wet etching. This last step ends the buried plate region formation process and the final structure is shown in FIG. 1H. Any attempt to create buried plate region 19 by mean of an arsenic ion implantation step would fail because the deep trench is too minute and such implantation would require an inaccessible level of implant energy.
To understand the specific buried plate region process requirements, it is necessary to consider the structure 10 at a much further stage of the chip fabrication process. FIG. 2 shows structure 10 after gate conductor stack and source/drain regions completion. At this stage, with regard to the structure depicted in FIG. 1H, the SiO2/Si3N4 pad layer 12/13 has been eliminated and the trench 14 has been filled with doped polysilicon to form the first electrode of the cell capacitor. The polysilicon fill is electrically isolated from the substrate 11 by a 30 nm thick TEOS SiO2 collar layer 21 on its upper part and a 5 nm thick reoxidized silicon nitride layer 22 on its lower part. The latter layer forms the dielectric film of the cell capacitor. Still very schematically, two ion implantation steps are performed to define first a 1000 nm thick N-well 23, then a 800 nm thick P-well region 24. The second electrode of the cell capacitor is thus formed by the buried plate region 19, the N-well region 23 being used to interconnect all the buried plate regions of the chip. Finally, after gate conductor stack 25 and source/drain regions 26 formation, an IGFET bearing numeral 27 visible in FIG. 2 is created.
It is essential to chip reliability that the top of BP region 19 is located below and preferably at about 450 nm from the P-well/N-well junction. If the top of BP region 19 extends in the P-well region, a parasitic NPN transistor is then constituted by the N type drain region 26 of IGFET 27, the P-well 24 and the N+ BP region 19 that will degrade the storage operation. If the top of BP region 19 is below the bottom of N-well region 23, the BP region 19 could not be biased via the N-well 23 any longer and undesired voltage breakdown would occur during storage operation. As a consequence, it is recommended to have the top of the BP region 19 centered in the N-well at 1250 nm+-450 nm from silicon substrate 11 surface. The best case is when the top of BP region 19 slightly overlaps the bottom of collar layer 21 as made apparent in FIG. 2. If we take into account ASG film wet etch and out diffusion steps, the targeted value for photoresist etch is 1500 nm+-250 nm which corresponds to the value indicated in FIG. 1D.
The step of partially removing the photoresist material of layer 16 is thus essential to the whole buried plate region formation process because the remaining photoresist determines the protected portions of the ASG film to remain which in turn defines the BP region during the out diffusion step.
However, Applicant's inventors have discovered that instead of improving the photoresist etch step described by reference to FIG. 1D, the same result could be obtained through the improvement of the ASG film deposition step. Surprisingly, they pointed out the determining role of two parameters: the ASG film thickness and As concentration in the ASG film and more particularly of their uniformity, trench to trench, wafer to wafer and lot to lot.
Now turning to FIG. 3, the vertical reactor referenced 30 is essentially comprised of outer and inner walls 31 and 32 affixed upon a base 33. The temperature inside the reactor is controlled by a five heating zone element 34. A boat 35 containing the wafers 36 is mounted on a pedestal 37 in the central part of the base 33. An exhaust pump 38 is connected to the interior volume of the reactor by adequate piping. Reactor 30 further includes a TEASAT bubbler system 39 and a TEOS vapor delivery system 40. The reactor has two separated bottom gas injections for the TEOS and TEASAT lines at opposite side of the base 33. The TEOS vapor delivering system and the TEASAT bubbler are manufactured by Schumacher, Carlsbad, Calif., USA, which also supplies the TEASAT precursor. The TEOS gas is produced by heating liquid TEOS in an ampule at 65.degree. C. (supplied by OLIN HUNT, Seeward, Ill., USA). As far as TEASAT is concerned, vapor is fabricated by nitrogen bubbling in a 45.degree. C. heated liquid TEASAT ampule (manufactured by Schumacher). The diameters of the injection lines are equal to 0.25 inch. TEOS and TEASAT precursors delivery gas lines and nitrogen bubbling line are all heated up to 80.degree. C. to avoid gas condensation into liquid droplets before injection. For this deposition step, the process parameters are:
Bubbler Temp.: 45.degree. C. Process Temp.: 650.degree. C. Sheet Res. (max.): 150 Ohm/sq Dep. rate: 1.1 nm/min ASG film thickness: 45 nm TEOS flow: 20 sccm TEAS/N2 flow: 20 sccm Press.: 600 mT Boat (.37 inch pitch): 25 wafers
This sheet resistivity of 150 Ohm/sq which is the greatest acceptable value corresponds to an As atom concentration of about 5E19 at/cm3 in the ASG film 15 . The conventional ASG film deposition process mentioned above produces ASG film side wall thickness of 45 nm (+-15% wafer to wafer, +-7% within a same wafer) and an As concentration varying between 1E21 and 2E21. As a global result, the junction depth and the As concentration in BP region 19 can be out of specifications (below the desired values of 0.25 .mu.m and 5E19 at/cm3 respectively). Moreover, the top location of BP region 19 can be not well centered. As emphasized above, the BP region 19 top location spreads so much within the chip with the conventional process that this is dramatic for chip reliability.
More generally, according to their works they arrived to the conclusion that an adequate ASG film deposition step should meet the following criteria:
1--An excellent conformality between top trench surface and trench side wall. PA1 2--A very good thickness uniformity. PA1 3--A very good sheet resistance uniformity.
Moreover, this must be obtained with the maximum reproducibility trench to trench, wafer to wafer and lot to lot. A direct consequence of this uniformity improvement is a significant increase in the product wafer batch size. As a matter of fact, every variation of these two key parameters provides undesired variations of other important process parameters at subsequent steps: photoresist fill and etch, ASG film etch, and finally in the buried plate region formation. Finally, if these key parameters are not with specifications, other problems can be noticed. If ASG film thickness is too high, some part of the ASG film may be left at the bottom of the trench after stripping, then, the cell capacitance is too low and would involve a retention time problem (ONO dielectric material instead of NO). Moreover, because the increased depth of the moat 17 due to the necessary over etch, the top location of BP region 19 will be too low. On the other hand, if the As concentration is too low (not enough doping species), the BP region 19 is not well formed and the cell capacitor breakdown occurs at lower VT (threshold voltage).